1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. More specifically, the present invention relates to a semiconductor device having a plurality of transistors comprising gate insulating films of different film thickness, and a method for manufacturing such a semiconductor device.
2. Background Art
Concurrent with the advance of the down-sizing technology of semiconductor integrated circuits in recent years, the dimension of an element has been reduced, and a larger number of elements have been able to be mounted in a chip. Therefore, an integrated-circuit device referred to as SoC (system on chip) that can individually realize functions conventionally realized using a plurality of element has been widely used.
In the logic circuit portion of an SoC, it is required to lower the driving voltage for reducing power consumption. At the same time, in order to prevent the lowering of the driving current due to the reduction of the driving voltage, the thickness of the gate insulating film of an MOSFET (metal oxide semiconductor field effect transistor) has been reduced.
On the other hand, the MOSFET used in the peripheral circuit portions accompanying inputs and outputs must be directly driven by an external voltage. Therefore, a high withstand voltage is required in the MOSFET used in the peripheral circuit portions, and a gate insulating film having a large film thickness to some extent is required. For example, a thick gate insulating film having a thickness of about 6.0 nm to 10 nm has been used in a high-withstand-voltage 3.3V MOSFET.
When a logic circuit portion and a peripheral circuit portion are formed in a semiconductor device, the gate insulating films of the different thickness require to be formed in these circuit portions on a substrate. One of the methods for forming gate insulating films of different thickness is as follows:
First, a silicon oxide film of a thickness equivalent to the difference between the thickness of the thick gate insulating film of the high-withstand-voltage MOSFET for the peripheral circuit and the thickness of the thin gate insulating film of the MOSFET for the logic circuit. Thereafter, the silicon oxide film on the portion for forming the MOSFET for the logic circuit is selectively removed. Then, heat-treatment is performed to grow the silicon oxide film by the thickness of the gate insulating film of the MOSFET for the logic circuit. At this time, the gate oxide film of the high-withstand-voltage MOSFET for the peripheral circuit is also grown. Thus, the gate insulating films having different thickness are formed (for example, refer to Japanese Patent Laid-Open No. H11-177047 (1999) and No. H11-289061 (1999)).
As another method, the method as described below has also been proposed. First, in the same manner as the process for forming an ordinary MOSFET, a gate insulating film of a thickness equal to the thickness of the insulating film of the high-withstand-voltage MOSFET for the peripheral circuit, and a gate electrode are formed in each of the logic circuit portion and the peripheral circuit portion. Thereafter, ion implantation and heat treatment for the formation of a diffusion layer are performed. Then, an interlayer insulating film is formed on the entire surfaces of the gate insulating film and the gate electrode. Next, the peripheral circuit portion is coated with a resist film, and the gate electrode and the gate insulating film in the logic circuit side are removed from the interlayer insulating film. Thereby, a trench of the width of the gate electrode is formed in the interlayer insulating film. Then, a thin gate insulating film of the MOSFET for the logic circuit is formed in the trench, and a gate electrode is buried to form an MOSFET for the logic circuit. Here, since the gate insulating film and the gate electrode initially formed in the region for the logic circuit are removed later, these are called dummy gates (for example, refer to Japanese Patent Laid-Open No. 2000-100966 and No. 2000-195966).
With the miniaturization of semiconductor devices in recent years, the further reduction of the thickness of gate insulating films has been demanded. However, in the case when a silicon oxide film is used as a gate insulating film, if the thickness thereof is 2 nm or less, leak current increases resulting in the increase of power consumption. Since such a thin silicon oxide film is formed of several atomic layers, it is difficult to form evenly, and since a strict manufacturing control is required to improve the uniformity of film thickness, mass production becomes difficult.
Therefore, in order to produce finer elements and reduce power consumption, the use of a high-dielectric-constant film (hereafter referred to as high-k film) as a gate insulating film has been studied. The high-k film can be formed thicker than the silicon oxide film, while maintaining the effective film thickness that determines the transistor current sufficiently thin, and can inhibit the increase of power consumption.
As such an SoC, there has been proposed a semiconductor device that uses a high-k film as the gate insulating film of an MISFET (metal insulator semiconductor field effect transistor) for the logic circuit, and a thick silicon oxide film and a high-k film as the gate insulating film for the peripheral circuit. When this semiconductor device is formed, a silicon oxide film is first formed on the entire surface of a substrate using an ordinary method. Thereafter, the silicon oxide film in the region for forming the MISFET for the logic circuit is removed, and then, a high-k film is formed on the entire surface using a CVD method or the like. Thereby, the gate insulating films having different thickness between the peripheral circuit side and the logic circuit side can be formed (for example, refer to Japanese Patent Laid-Open No. 2002-164439).
MISFETs used in the logic circuit portion of SoC are classified into a low operating power (LOP) version that requires relatively high-speed operation, a low stand-by power (LSTP) version, and the like. Some SoC use either an MISFET for LOP or an MISFET for LSTP in the logic circuit portion, and an MISFET for a high withstand voltage in the peripheral circuit portion. In recent years, however, the number of semiconductor devices using both MISFETs for LOP and LSTP in the logic circuit portion, and an MISFET for a high withstand voltage in the peripheral circuit portion is increasing. Such semiconductor devices are useful when used in mobile phones or the like, which require both the operation speed for a long time operated by batteries and high performance, and the demand for such semiconductor devices will further be increased in future.
In such SoC carrying an MISFET for LOP, an MISFET for LSTP, and an MISFET for a high withstand voltage in one chip, the thickness of the gate insulating films in these MISFETs is different from each other. The ITRS (The International Technology Roadmap for Semiconductors) recommends that the EOT (film thickness converted to the thickness of a silicon oxide film) of a gate insulating film of the MISFET for LOP in a 65-nm technology node is 1.0 nm to 1.4 nm, and the EOT of the MISFET for LSTP is 1.2 to 1.6 nm as the target values.
In this case, the difference between the thickness of MISFETs for LOP and LSTP is 0.2 nm to 0.4 nm. When an SoC having both MISFETs for LOP and LSTP is formed, there is considered the use of a method as described above wherein a thermal oxide film is formed, the thermal oxide film in the side to form a thin gate insulating film is removed, and a thermal oxide film is formed again. However, a silicon oxide film easily permeates oxygen, and the film is rapidly grown in the later thermal oxidation. Therefore, the difference in the thickness of gate insulating films between the MISFET for LOP side and the MISFET for LSTP side cannot be controlled to be as small as 0.2 nm to 0.4 nm.
The use of, for example, a method as described above wherein a trench is formed in an interlayer insulating film using a dummy gate, and a high-k film is formed in the trench is also considered. However, it is difficult to control the thickness of the high-k films formed using a CVD (chemical vapor deposition) method so as to have a thickness difference of about 0.2 to 0.4 nm. It is also considered to control the thickness difference utilizing a silicon oxide film as the gate interfacial film formed under the high-k film. However, as described above, it is difficult to control the thickness of a silicon oxide film. Furthermore, the formation of three gate insulating films is required when three kinds of MISFETs, i.e., MISFET for LOP, MISFET for LSTP, and MISFET for high withstand voltage for peripheral circuits; however, in this case, since the formation and removal of the dummy gate must be repeatedly performed, the number of steps increases resulting in lowered productivity. Furthermore, since the high-k film initially formed is undergone, in addition to the heat treatment of the PDA (post deposition annealing) step for itself, heat of the PDA step for the high-k film subsequently formed, it becomes difficult to control the film thickness and to secure reliability.
Alternatively, there can also be considered a method wherein a silicon oxide film is formed on the entire surface of a substrate, the silicon oxide film in the logic-circuit side is removed, and then a high-k film is formed on the entire surface using a CVD method or the like. In this case, however, it is also difficult to form a silicon oxide film of a thickness equivalent to the thickness difference between the insulating films of 0.2 to 0.4 nm.